VLSI & Digital Systems • VLSI • ECE • Embedded Systems • Final Year Capstone (7th/8th Sem)
FPGA Neural DSP Accelerator
A dedicated digital hardware coprocessor designed on a Xilinx FPGA. Implements pipelined Multiply-Accumulate (MAC) DSP blocks for real-time edge audio feature extraction and 1D convolution with zero soft-processor overhead.
Hardware Bench Preview
Component Bill of Materials (BOM)
Total: ₹4,280 1. Xilinx Spartan-6 / Spartan-7 FPGA Development Board
Qty: 1 ₹2,850
2. Platform USB JTAG Cable & Programmer Interface
Qty: 1 ₹650
3. I2S Master Audio Codec (PCM5102A DAC / INMP441)
Qty: 1 ₹320
4. 1.3" SPI TFT Display for On-Chip Register Telemetry
Qty: 1 ₹280
5. High-Speed Logic Analyzer Test Header Pinout
Qty: 1 ₹180
Academic Deliverables Included
- ✓ University Major Project Dissertation with RTL register schematics and FSM state charts
- ✓ Clean synthesizable Verilog source code (.v) and comprehensive testbench suite (.tb)
- ✓ Vivado / ISE synthesis reports, timing constraint files (.xdc), and power dissipation tables
- ✓ Examiner Viva defense presentation with DSP math breakdown and RTL walkthrough
Bench Testing Benchmarks
- • Synthesizable Verilog HDL with static timing closure achieved at 100MHz clock
- • 8-stage parallel MAC pipeline reducing inference latency by 14x vs ARM MCU
- • RTL simulation testbench verified in ModelSim / Vivado with bit-exact vectors
- • On-chip BRAM utilization under 65% leaving room for custom student modifications