Grain-PRG 45: 128-Bit Stream Cipher ASIC on NanGate 45nm
8-bit parallel combinational unrolling stream cipher ASIC running at 800 Mbps (100 MHz) with NanGate 45nm physical signoff and zero DRC violations.
System Overview & Abstract
An autonomous lightweight cryptographic engine engineered at the silicon level for hardware-constrained IoT security. Implemented on the NanGate 45nm Open Cell Library (with a SkyWater 130nm baseline flow), it accelerates the eSTREAM Grain-128 stream cipher using 8-bit parallel combinational unrolling. By predicting 8 consecutive cipher states in pure wire logic without intermediate registers, the architecture delivers 8 bits (1 byte) per clock cycle—achieving 800 Mbps throughput at 100 MHz (and up to 6.4 Gbps at 800 MHz max frequency) while consuming only 324.8 µW across an ultra-compact 2,376 µm² silicon area with 0 DRC violations.
OpenROAD Physical Design & Silicon Layouts
Actual signoff layout captures from OpenROAD physical design, standard cell rows, and static timing workspace.
NanGate 45nm — Full Chip Routed Layout
Complete silicon die layout in OpenROAD showing 1,106 standard cells, PDN straps, and 6,808 routing vias with 0 DRC violations.
OpenROAD GUI Environment & Timing Inspector
Physical design environment displaying core boundary, standard cell placement density, and OpenSTA static timing workspace.
Gate-Level Detail & Metal Interconnects (MUX2_X1)
Nanometer-scale gate inspection highlighting individual MUX2_X1 multiplexer cells, contact cuts, and Metal1–Metal5 interconnects.
3-Way Benchmark Comparison: Reference Papers vs. 45nm ASIC
Rigorous signoff benchmark comparing baseline serial literature (Hell et al.), modern 4-bit parallel research (Amsavalli et al.), and our NanGate 45nm 8-bit parallel chip.
| Parameter / Metric | Serial Paper (Hell et al.) | Parallel Paper (Amsavalli '21) | Our 45nm ASIC (Grain-PRG 45) | Improvement / Delta |
|---|---|---|---|---|
| Architecture | Serial (1 bit / cycle) | 4-Bit Parallel Unrolled | 8-Bit Parallel Combinational Unrolling | 8× Data Rate Acceleration |
| Cycles per 128-Bit Block | 128 cycles | 32 cycles | 16 clock cycles | 8× Latency Reduction |
| Throughput @ 100 MHz | 100 Mbps (0.1 Gbps) | 400 Mbps (0.4 Gbps) | 800 Mbps (0.8 Gbps) | 8× vs Serial / 2× vs 2021 Paper |
| Max Freq (Fmax) & Throughput | 300 Mbps @ ~300 MHz | 1,600 Mbps @ 400 MHz | 6,400 Mbps (6.4 Gbps @ 800 MHz) | 4.0× Speedup vs 2021 Paper |
| Silicon Core Area | ~14,000 µm² (180nm) | ~5,200 µm² (90nm) | 2,375.91 µm² (NanGate 45nm) | 54.3% Area Saving vs 2021 Paper |
| Total Power Consumption | ~1.85 mW (1,850 µW) | ~0.850 mW (850 µW) | 0.3248 mW (324.8 µW) | 61.8% Power Saving vs 2021 Paper |
| Energy per 128-Bit Block | 2.368 nJ / block | 0.272 nJ / block | 0.0518 nJ (51.8 pJ) / block | 5.25× Energy Saving vs 2021 Paper |
| Physical DRC Violations | N/A | N/A | 0 DRC Violations (Clean Signoff) | Tapeout Ready |
NanGate 45nm Standard Cell Breakdown (1,106 Total Cells)
Open-Source Silicon & EDA Toolchain Deliverables
Zero extra hardware components purchased. 100% open-source silicon tapeout flow validated on NanGate 45nm & SkyWater 130nm PDKs.
| Deliverable / Toolchain Package | Qty | Procurement Rate | Subtotal | License / Ecosystem |
|---|---|---|---|---|
| NanGate 45nm Open Cell Library (NangateOpenCellLibrary_typical.lib) | 1 | ₹0 (Free) | ₹0 (Open Source) | Open-Source PDK |
| SkyWater 130nm Open PDK (sky130_fd_sc_hd Baseline Flow) | 1 | ₹0 (Free) | ₹0 (Open Source) | Open-Source PDK |
| Yosys Logic Synthesis Suite (1,106 Standard Cells Netlist) | 1 | ₹0 (Free) | ₹0 (Open Source) | Open-Source EDA |
| OpenROAD Automated Physical Design Flow (DEF/GDSII P&R, 0 DRC) | 1 | ₹0 (Free) | ₹0 (Open Source) | Open-Source EDA |
| OpenSTA Signoff Static Timing & Power Analysis Engine | 1 | ₹0 (Free) | ₹0 (Open Source) | Open-Source EDA |
| Icarus Verilog Simulation Suite & GTKWave Signal Dump | 1 | ₹0 (Free) | ₹0 (Open Source) | Open-Source EDA |
| Total Component Expenditure: | ₹0 (100% Open EDA) | |||
Request Custom VLSI & RTL Package
Need a custom cryptographic engine, stream cipher, or ASIC core? Send your problem statement or RTL specs for a feasibility review, testbench suite, and OpenROAD layout.